Fin field effect transistor (FinFET) devices have fast switching times and high current densities, and are often a desired transistor device architecture. A FinFET device typically comprises a source, a drain and one or more fin-shaped channels between the source and the drain. A gate electrode positioned over the fin(s) regulates electron flow between the source and the drain and is often defined by optical lithography.
FinFETS may be fabricated by following either a gate first or gate last approach. In the gate last approach, a dummy gate is initially used to pattern the source and drain (S/D) regions. Following the dummy gate patterning and S/D formation, interlayer dielectric (ILD) deposition is carried out to fill in between the fins and the gates. Then, the dummy gate is removed followed by replacement gate patterning.
As feature sizes of the FinFET devices get increasingly smaller, accurately and consistently defining the device features becomes more difficult. Scaling fin or channel width is another challenge for FinFET manufacturing. For schemes where the fins are formed before gate patterning, thin fins must survive gate (possibly removable or dummy gate) and spacer processing, which often involve aggressive etching processes.
The manufacturing of FinFET structures, which are 3D-structures, involves different types of processes which are topography-dependent. Examples of such processes are material deposition or growth processes, especially epitaxial growth processes, etching or other removal processes, illumination or irradiation, implantation processes, etc. The efficiency of these processes typically deteriorates when topography increases.
In the future, the integration of 2D transistor structures with 3D transistor structures may be required. The dependency of manufacturing steps to topography, for instance expressed as dependency on aspect ratio of device features, would require a relatively independent processing of 2D and 3D devices, which is complex and costly, such that solutions in this field are rare or non-existing.
Typical FinFET processing requires certain processing steps at elevated temperatures, for instance when performing a source/drain anneal step. This limits the choice of materials used therein.
Currently, there is also a need for manufacturing methods which allow the integration of different channel materials as, for example, Si channel, SiGe channel, Ge channel, and III-V channel materials.
In US patent application US2012/0313170 A1 (Chang), a method for fabrication of FinFET devices is disclosed. Chang discloses providing patterned hard mask on an active layer on top of a buried oxide layer of a silicon on insulator substrate, the patterned hard mask defining eventual fin regions. Then a dummy gate is placed over the fin hard mask. Later in the fabrication process, the dummy gate is removed, thereby revealing the underlying fin hard mask and active layer. The fin hard mask is then used to pattern the fins within the active layer. The hard mask has relatively large thickness, such that the presence thereof during the FinFET processing introduces a relatively large topography.